Astera Labs Targets AI's Connectivity Wall With Scorpio, Leo and COSMOS

Four walls limiting tokens per dollar

In a blog post, Mohan says AI has entered the inference era in earnest, and that data center operators now talk less about the "AI model" and more about the "AI factory". In his view, the winning approach must deliver economic efficiency as well as peak performance and reliability. He says four walls constrain tokens per second and, more importantly, tokens per dollar.

• Wafer Wall: a gigawatt of AI compute needs roughly 55,000 logic wafers and 170,000 memory wafers. By 2030, AI wafer demand is expected to have a 1-4 million advanced node wafer shortfall.
• Power Wall: the U.S. grid is expanding linearly while AI demand expands exponentially. Developers face a 34% net power shortfall through 2028 (roughly 32 GW), and 70% of standard grid connection requests are withdrawn due to years-long delays.
• Memory Wall: at AI Infra Summit 2026, analyst Jim Handy reported a 250% Y/Y jump in DRAM prices as inference and agentic workloads push KV cache demand higher.
• Connectivity Wall: in a large GPU cluster, the interconnect determines how much compute does useful work.

Why connectivity is the lever

Mohan writes that three of the walls are physically fixed, since nobody can manufacture, generate or buy past wafer, power or memory scarcity on a timeline that matters this cycle. Connectivity is the exception. Each new GPU generation adds PFLOPS and memory bandwidth, which raises the demands on the fabric feeding it. Otherwise, he says, million-dollar accelerators stall waiting on data instead of generating tokens.

The company's argument is that better utilization of existing infrastructure works as new capacity. It extracts more useful work from the same silicon, power and budget.

Products on show at OCP 2026

Astera Labs will run live demos at OCP 2026, led by the Scorpio X-Series 320L Smart Fabric Switch, which it calls the industry's highest-radix PCIe scale-up switch. According to the company, Scorpio's Hypercast and In-Network Compute features boost collective operations by up to 2x by creating optimized pathways and cutting communication overhead. A footnote says the figure reflects at least a 50% reduction in AllReduce collective operation latency versus traditional Ring AllReduce, based on internal analysis, and that results may vary with workload, system configuration and cluster size.

The recently released Leo X-Series Smart Memory Controller pairs with Scorpio switches to form a fabric-attached memory tier for KV cache offload. Early data shows a 22% increase in GPU utilization, or 22% more tokens per second, from this tier alone, according to Astera Labs. The second-generation Leo E-Series and P-Series controllers offer CPU-attached CXL memory expansion, sharing and pooling, and can reuse recycled DDR4 memory while DDR5 supply remains extremely limited.

Software, low-power signal conditioning and open standards

COSMOS, the company's software framework, lets customers customize Astera products, tune system performance and bring up complex systems with deep debug capabilities. It also provides fleet-scale telemetry. In Scorpio X-Series fabrics it configures and manages Hypercast and In-Network Compute. Astera Labs says COSMOS has been adopted by multiple customers and will feature in every OCP 2026 demonstration.

For power-limited sites, the recently released Taurus Smart Signal Conditioners offer footprint-compatible choices between Smart Retimers and Smart Redrivers for Ethernet, ESUN and UALink. Where signal amplification is enough, designers can pick the lower-power redriver. The company will also show copper and optical roadmaps: copper for dense links within the rack, and optical to extend PCIe fabrics beyond the box and rack.

Astera Labs calls the OCP Global Summit its flagship annual event and says it sits on the boards of standards bodies such as UALink and CXL. Its "AI Your Way" approach promises interconnect built for customers' workloads regardless of accelerator, protocol or physical media.

What it means for operators

For operators facing tight supply of chips, power and memory, the pitch is to raise output from hardware already installed rather than rely on more accelerators. The performance figures come from Astera Labs itself and from early data, so independent results will matter. Visitors to the booth at OCP 2026 can see the demos first-hand.