IBM and Siemens team up to prepare nanostack transistors for production
IBM and Siemens have announced a research collaboration to advance nanostack, the three-dimensional transistor architecture IBM unveiled earlier this year. The aim is to develop the design, simulation and lithography techniques needed to move the technology toward production.
- IBM and Siemens announced a research collaboration on October 14, 2026 to advance IBM's nanostack transistor architecture.
- Siemens contributes EDA, process simulation, lithography optimization and manufacturing software expertise.
- Nanostack is a 3D, nanosheet-based design with nearly 100 billion transistors in a fingernail-sized space at the 7 angstrom node, according to IBM.
- The work includes virtual models to optimize designs and address fabrication challenges before chips are built.
- The goal is to prepare nanostack for manufacturing at scale, including generations beyond 7 angstrom.
What the collaboration covers
According to IBM, the work combines its semiconductor device innovation with Siemens' expertise in electronic design automation (EDA), process simulation, lithography optimization and advanced manufacturing software. The announcement was made from Albany, NY, on October 14, 2026.
IBM says it demonstrated the viability of the nanostack architecture earlier this year, but that additional advances are needed to prepare it for manufacturing and production at scale. Together, the companies will work on design, simulation and lithography techniques for this and future nanostack generations beyond the current 7 angstrom node.
Part of the effort is building advanced virtual models of nanostack. These are meant to model performance, optimize designs and address fabrication challenges before chips are built.
What nanostack is
IBM describes nanostack as the industry's first known three-dimensional, nanosheet-based design. It vertically stacks and staggers transistors to fit more of them onto a chip. At the current 7 angstrom node, IBM says this allows nearly 100 billion transistors in a space the size of a fingernail.
The design also allows different material combinations within each stacked layer, so that the performance and power efficiency of each transistor can be optimized independently of the other. According to IBM, these innovations power substantial leaps in energy efficiency, performance and SRAM scaling.
What the companies say
Huiming Bu, Vice President of Silicon Technology R&D at IBM, called nanostack "a scalable transistor platform designed to shift device scaling from 2D to 3D." He described it as "a path forward for the logic scaling needed to support AI and other emerging technologies over the coming decade."
Ankur Gupta, Executive Vice President, EDA IC Portfolio at Siemens, said that scaling semiconductors into the angstrom era "demands tightly coupled co-optimization between device physics, EDA design and manufacturing software, and manufacturing." He also said the collaboration to advance virtual modeling, simulation, lithography and design software optimizations is "truly pioneering."
What it means
The announcement does not give a production date, customer commitments or performance targets for future nodes. What it does set out is the work still ahead: turning a demonstrated architecture into something that can be designed, simulated and manufactured reliably at scale.
The companies say they aim to accelerate technology development cycles and advance the manufacturing foundation needed to bring nanostack toward production. For the chip industry, the focus on addressing physical limitations early through virtual models points to design and simulation tools as a key part of making 3D transistor scaling practical.
