SEI Weighs Which Hardware Will Test DARPA MOCHA's Compilers

What DARPA MOCHA is trying to fix

MOCHA stands for Machine Learning and Optimization-guided Compilers for Heterogeneous Architectures. It sits in DARPA's Information Processing Techniques Office and is managed by Dr. Howard Shrobe. According to the SEI post, the program targets a long-standing problem: traditional compilers were not designed to generate efficient machine code for mixed systems of CPUs, GPUs and application accelerators.

Today, developers usually hand-write specialized code and rely on vendor-tuned libraries to use a new accelerator. The post says this is slow and expensive and encourages vendor lock-in, since an application written against a proprietary library must be rewritten to move to other hardware. Extending a compiler to a new computational element is also manual work that only compiler experts can do.

MOCHA's hypothesis is that data-driven methods, machine learning and advanced optimization can let compilers adapt to new hardware rapidly and with minimal human intervention. The post says performance models of the target hardware drive every step of compilation, and that building them by hand is the central bottleneck. Generating them by measuring code on real hardware and mining architectural documentation could sharply cut the cost of supporting a new device. A guiding principle is ALARA, keeping human involvement As Low As Reasonably Achievable.

The SEI's role and the evaluation machine

The SEI's Advanced Computing Lab, part of its AI Division, supports the government team with a focus on test and evaluation. It gathers and assesses options for the program manager, maintains the evaluation machine where the hardware is integrated, and builds the measurement methodology used to compare results from the performer teams fairly. The performers develop the compiler technology.

DARPA plans for MOCHA to include six distinct computing types by the end of the effort. The post defines a computing type by a distinct instruction set and programming model, not by hardware architecture alone. On that definition, a data-center GPU, a device combining FPGA fabric with a spatial AI-engine array, a long-vector processor, and a RISC-V-plus-dataflow AI accelerator count as four different types.

Any chosen hardware must physically fit the evaluation machine, a workstation-class tower built around an Intel Core Ultra 9 285K. It brings AVX2 SIMD on the CPU, an integrated Xe GPU, a neural processing unit and PCIe 5.0 connectivity, and it already holds an NVIDIA RTX 4500 Ada card as a baseline reference. Candidates therefore need to be PCIe cards that fit the chassis, power and cooling of a single tower.

Five selection factors

The team weighed availability, maturity, affordability, programmability and the ability to host the device. Availability and hosting ruled out wafer-scale engines, reconfigurable-dataflow systems that ship only as complete servers, and cloud-only accelerators. Affordability excluded parts that cost more than the rest of the machine combined.

The post calls programmability the most influential factor, in particular the state of compiler and multi-level intermediate representation (MLIR) support. MOCHA performers overwhelmingly build on the LLVM and MLIR ecosystem. If a target already has an MLIR or LLVM path, performers can reach it and focus on research such as retargetable code generation, learned cost models and optimization selection. A sealed target reachable only through a vendor's pre-tuned inference stack may offer little for a MOCHA compiler to work against.

The working short list

The short list spans GPUs, spatial FPGA-plus-AI-engine devices, a vector processor, several AI accelerators and networking silicon. The entries described in the post include:

• AMD Instinct MI350P: a data-center GPU (CDNA 4) programmed through ROCm/HIP, with MLIR support via rocMLIR and the Triton path. It is a newly announced PCIe form factor.
• AMD Versal ACAP: combines an FPGA fabric, a spatial AI-engine array and ARM cores. The open mlir-aie/IRON toolchain and Peano LLVM back end make the AI-engine array a close-to-metal MLIR target.
• Intel Data Center GPU Max 1100: an Xe-HPC GPU programmed through oneAPI/SYCL, and the only Max-series part offered as a PCIe card.
• Intel Gaudi 3: an AI accelerator with matrix and VLIW-SIMD tensor engines. Its graph compiler builds MLIR-based fused kernels but remains proprietary.
• Intel Xe iGPU: the integrated GPU already in the evaluation machine, described as a zero-cost portability target.
• NEC SX-Aurora TSUBASA: a long-vector processor on a PCIe card with an upstream LLVM back end.
• Qualcomm Cloud AI 100: listed next, but the available text of the post ends before its description.

What it means

The post frames hardware choice as a design decision for the whole program, shaping the next two years of the effort. Open, low-level access favors the program's goal of quickly supporting new hardware, while closed vendor libraries work against it. For compiler researchers, the selected set will define the targets on which MOCHA results are measured and compared.